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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Rev. 02 -- 6 August 2009 Product data sheet
1. General description
The NXP Semiconductors SE98A measures temperature from -40 C and +125 C with JEDEC Grade B 1 C accuracy between +75 C and +95 C communicating via the I2C-bus/SMBus. It is typically mounted on a Dual In-Line Memory Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Thermal Sensor Component specification. The SE98A thermal sensor operates over the VDD range of 1.7 V to 3.6 V. The SE98A does not include the 2 k SPD and is designed for custom DIMM where larger SPD is required. The Temp Sensor (TS) consists of an Analog-to-Digital Converter (ADC) that monitors and updates its own temperature readings 8 times per second, converts the reading to a digital data, and latches them into the data temperature registers. User-programmable registers, such as Shutdown or Low-power modes and the specification of temperature event and critical output boundaries, provide flexibility for DIMM temperature-sensing applications. When the temperature changes beyond the specified boundary limits, the SE98A outputs an EVENT signal using an open-drain output that can be pulled up between 0.9 V and 3.6 V. The user has the option of setting the EVENT output signal polarity as either an active LOW or active HIGH comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. The EVENT output can even be configured as a critical temperature output. The SE98A supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identify of the device. Three address pins allow up to eight devices to be controlled on a single bus. The SE98A is an improved SE98 and is comparable to the thermal sensor in the SE97 but with voltage range of 1.7 V to 3.6 V.
2. Features
I JEDEC (JC-42.4) TS3000B1 DIMM 0.5 C (typ.) between 75 C and 95 C temperature sensor I Optimized for voltage range: 1.7 V to 3.6 V I Shutdown current: 0.1 A (typ.) and 5.0 A (max.) I 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz I SMBus ALERT and TIMEOUT (programmable) I 11-bit ADC Temperature-to-Digital converter with 0.125 C resolution
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Operating current: 250 A (typ.) and 400 A (max.) Programmable hysteresis threshold: 0 C, 1.5 C, 3 C, 6 C Over/under/critical temperature EVENT output B grade accuracy: N 0.5 C/1 C (typ./max.) +75 C to +95 C N 1 C/2 C (typ./max.) +40 C to +125 C N 2 C/3 C (typ./max.) -40 C to +125 C I ESD protection exceeds 2000 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Available packages: TSSOP8, HWSON8 (PSON8 VCED-3) and HXSON8 I I I I
3. Applications
I I I I DDR2 and DDR3 memory modules Laptops, personal computers and servers Enterprise networking Hard disk drives and other PC peripherals
4. Ordering information
Table 1. Ordering information Topside mark S98A 98A 8AL Package Name TSSOP8 HWSON8 HXSON8 Description plastic thin shrink small outline package; 8 leads; body width 4.4 mm plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm Version SOT530-1 SOT1069-1 SOT1052-1 Type number SE98APW SE98ATP[1] SE98ATL
[1]
Industry standard 2 mm x 3 mm x 0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm x 4 mm pitch tape 4 k quantity reels.
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
2 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
5. Block diagram
SE98A
TEMPERATURE REGISTER CRITICAL ALARM TRIP UPPER ALARM TRIP LOWER ALARM TRIP CAPABILITY MANUFACTURING ID DEVICE/REV ID SMBus TIMEOUT/ALERT CONFIGURATION * * * * * * * HYSTERESIS SHUT DOWN TEMP SENSOR LOCK PROTECTION EVENT OUTPUT ON/OFF EVENT OUTPUT POLARITY EVENT OUTPUT STATUS CLEAR EVENT OUTPUT STATUS 10 V OVERVOLTAGE
R 30 k to 800 k
POR BAND GAP TEMPERATURE SENSOR 11-BIT ADC
VDD
VSS
EVENT
SMBus/I2C-BUS INTERFACE
FILTER
SCL SDA
A0
A1
R 30 k to 800 k
A2 POINTER REGISTER
R 30 k to 800 k
002aad756
Fig 1.
Block diagram of SE98A
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
3 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
6. Pinning information
6.1 Pinning
terminal 1 index area A0 A1 A0 A1 A2 VSS 1 2 3 4
002aad757
1 2
8 7
VDD EVENT SCL SDA
8
VDD EVENT SCL SDA
SE98ATP
A2 VSS 3 4 6 5
SE98APW
7 6 5
002aad758
Transparent top view
Fig 2.
Pin configuration for TSSOP8
terminal 1 index area A0 A1 A2 VSS 1 2 3 4
Fig 3.
SE98ATL
Pin configuration for HWSON8
8 7 6 5
VDD EVENT SCL SDA
002aad910
Transparent top view
Fig 4.
Pin configuration for HXSON8
6.2 Pin description
Table 2. Symbol A0[1] A1 A2 VSS SDA SCL EVENT VDD
[1]
Pin description Pin 1 2 3 4 5 6 7 8 Type I I I ground I/O I O power Description I2C-bus/SMBus slave address bit 0 with internal pull-down I2C-bus/SMBus slave address bit 1 with internal pull-down I2C-bus/SMBus slave address bit 2 with internal pull-down device ground SMBus/I2C-bus serial data input/output (open-drain). Must have external pull-up resistor. SMBus/I2C-bus serial clock input/output (open-drain). Must have external pull-up resistor. Thermal alarm output for high/low and critical temperature limit (open-drain). Must have external pull-up resistor. device power supply (1.7 V to 3.6 V)
This input is overvoltage tolerant to support software write protection when applied to SPD.
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7. Functional description
7.1 Serial bus interface
The SE98A uses the 2-wire serial bus (I2C-bus/SMBus) to communicate with a host controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device can operate on either the I2C-bus Standard/Fast mode or SMBus. The I2C-bus Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus Fast-mode from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE98A uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most Significant Bit (MSB) transferred first, and a complete I2C-bus data is 1 byte. Since SCL and SDA are open-drain, pull-up resistors must be installed on these pins.
7.2 Slave address
The SE98A uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. The input of each pin is sampled at the start of each I2C-bus/SMBus access. The A0, A1 and A2 pins are pulled LOW internally. The A0 pin is also overvoltage tolerant, supporting 10 V software write protection when applied to the SPD that shares common address lines.
slave address MSB 0 0 1 1 A2 A1 LSB A0
R/W
X
fixed
hardware selectable
002aab304
Fig 5.
Slave address
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
5 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.3 EVENT output condition
The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT (CONFIG[7]) bands can be locked. Figure 6 shows an example of the measured temperature versus time, with the corresponding behavior of the EVENT output in each of these modes. Upon device power-up, the default condition for the EVENT output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can be read (CONFIG[4]) and cleared (CONFIG[5]).
* Advisory notification:
- NXP device: After power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. - Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. - Work-around: In order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. - SE98B will allow bit 2 or bit 0 to be changed even if bit 3 is set. If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output remains asserted during shutdown.
7.3.1 EVENT pin output voltage levels and resistor sizing
The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and would not affect the output. From the system perspective, there will be a practical limit. That limit will be the voltage necessary for the device monitoring the interrupt pin to detect a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another thing to consider is the value of the pull-up resistor. When a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the EVENT pin.
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
temperature (C) critical Upper Boundary Alarm Tamb Ttrip(u) - Thys
Tth(crit) - Thys Ttrip(u) - Thys
Ttrip(l) - Thys Lower Boundary Alarm Ttrip(l) - Thys time EVENT in Comparator mode
EVENT in Interrupt mode
software interrupt clear EVENT in `Critical Temp only' mode
(1)
(2)
(1) (3)
(4)
(3)(5)
*
(6) (4)
(2)
002aae324
Refer to Table 3 for figure note information.
Fig 6. Table 3. Figure note
EVENT output condition EVENT output condition EVENT output boundary conditions EVENT output Comparator mode Interrupt mode Critical Temp only mode Temperature Register Status bits Bit 15 Above Critical Trip 0 0 0 0 1 0 Bit 14 Above Alarm Window 0 0 1 0 1 1 Bit 13 Below Alarm Window 0 1 0 0 0 0
(1) (2) (3) (4) (5) (6)
Tamb Ttrip(l) Tamb < Ttrip(l) - Thys Tamb > Ttrip(u) Tamb Ttrip(u) - Thys Tamb Tth(crit) Tamb < Tth(crit) - Thys
H L L H L L
L L L L L H
H H H H L H
When Tamb Tth(crit) and Tamb < Tth(crit) - Thys the EVENT output is in Comparator mode and bit 0 of CONFIG (EVENT output mode) is ignored.
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.3.2 EVENT thresholds
7.3.2.1 Alarm window The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower temperature trip point as modified by hysteresis as programmed in the Configuration register. When enabled, the EVENT output triggers whenever entering or exiting (crossing above or below) the alarm window.
* Advisory notification:
- NXP device: The EVENT output can be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. - Competitor device: The EVENT output can be cleared only through the Clear EVENT bit (CEVNT). - Work-around: Only clear EVENT output using the Clear EVENT bit (CEVNT). - There will be no change to the NXP device. The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm Trip.
* Advisory notification:
- NXP device: Requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. - Competitor devices: Compares the alarm limit with temperature register at any time, so they get the EVENT output immediately when new UPPER or LOWER Alarm Windows and the EVENT output are set at the same time. - Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). - SE98B will compare alarm window and temperature register immediately after setting.
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.3.2.2
Critical trip The Tth(crit) temperature setting is programmed in the Critical Alarm Trip register (04h) as modified by hysteresis as programmed in the Configuration register. When the temperature reaches the critical temperature value in this register (and EVENT is enabled), the EVENT output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. The EVENT cannot be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip.
* Advisory notification:
- NXP device: Requires one conversion cycle (125 ms) after setting the Alarm Window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. - Competitor devices: Compares the Alarm Window with temperature register at any time, so they get the EVENT output immediately when new Tth(crit) and EVENT output are set at the same time. - Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before EVENT output is enabled and Event value is checked. 1. Set Tth(crit). 2. Doing something else (make sure that exceeds 125 ms). 3. Enable the EVENT output (EOCTL = 1). 4. Wait 20 s. 5. Read Event value. - SE98B will compare Alarm Window and temperature register immediately after setting.
7.3.3 Event operation modes
7.3.3.1 Comparator mode In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip resister if Tth(crit) only is selected). Reads/writes on the registers do not affect the EVENT output in comparator mode. The EVENT signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. The comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 Interrupt mode In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window threshold. After such an event occurs, writing a 1 to the Clear EVENT bit in the configuration register de-asserts the EVENT output until the next trigger condition occurs.
SE98A_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
In interrupt mode, EVENT asserts when the temperature crosses the alarm upper boundary. If the EVENT output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, EVENT asserts again. Because the temperature is greater than the critical temperature threshold, a Clear EVENT command does not clear the EVENT output. Once the temperature drops below the critical temperature, EVENT de-asserts immediately.
* Advisory notification:
- NXP device: If the EVENT output is not cleared before the temperature goes above the critical temperature threshold EVENT de-asserts immediately when temperature drops below the critical temperature. - Competitor devices: If the EVENT output is not cleared before or when the temperature is in the critical temperature threshold, EVENT will remain asserted after the temperature drops below the critical temperature until a Clear EVENT command. - Work-around: Always clear the EVENT output before temperature exceeds the critical temperature. - SE98B will keep EVENT asserted after the temperature drops below the critical temperature until a Clear EVENT command de-asserts EVENT.
7.4 Conversion rate
The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second--the faster the conversion rate, the faster the temperature reading is updated. The SE98A's conversion rate is at least 8 Hz or 125 ms.
7.4.1 What temperature is read when conversion is in progress
The SE98A has been designed to ensure a valid temperature is always available. When a read to the temperature register is initiated through the SMBus, the device checks to see if the temperature conversion process (Analog-to-Digital conversion) is complete and a new temperature is available:
* If the temperature conversion process is complete, then the new temperature value is
sent out on the SMBus.
* If the temperature conversion process in not complete, then the previous temperature
value is sent out on the SMBus. It is possible that while the SMBus Master is reading the temperature register, a new temperature conversion completes. However, this will not affect the data (MSB or LSB) that is being shifted out. On the next read of the temperature register the new temperature value will be shifted out.
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.5 Power-up default condition
After power-on, the SE98A is initialized to the following default condition:
* * * * *
Starts monitoring local sensor EVENT register is cleared--EVENT output is pulled HIGH by external pull-ups EVENT hysteresis is defaulted to 0 C Command pointer is defaulted to `00h' Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are defaulted to 0 C
* Capability register is defaulted to `0037h' for the B-grade and VHV capability * Operational mode: comparator * SMBus register is defaulted to `00h' 7.6 Device initialization
SE98A temperature sensors have programmable registers, which, upon power-up, default to zero. The open-drain EVENT output is default to being disabled, comparator mode and active LOW. The alarm trigger registers default to being unprotected. The configuration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT feature defaults to being enabled and can be programmed to disable. These registers are required to be initialized before the device can properly function. Except for the SPD, which does not have any programmable registers, and does not need to be initialized. Table 4 shows the default values and the example value to be programmed to these registers.
Table 4. Register 01h Registers to be initialized Default value 0000h Example value 0209h Description Configuration register
* * *
02h 03h 04h 22h 0000h 0000h 0000h 0000h 0550h 1F40h 05F0h 0000h
hysteresis = 1.5 C EVENT output = Interrupt mode EVENT output is enabled
Upper Boundary Alarm Trip register = 85 C Lower Boundary Alarm Trip register = -20 C Critical Alarm Trip register = 95 C SMBus register = no change
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.7 SMBus Time-out
The SE98A supports the SMBus time-out feature. If the host holds SCL LOW between 25 ms and 35 ms, the SE98A would reset its internal state machine to the bus idle state to prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out is disabled by writing a logic 1 to bit 7 of register 22h. Remark: When SMBus time-out is enabled, the I2C-bus minimum bus speed is limited by the SMBus time-out timer, and goes down to only 10 kHz. The SE98A has no SCL driver, so it cannot hold the SCL line LOW. Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless shutdown bit (SHMD) is set and turns off the oscillator.
7.8 SMBus ALERT
The SE98A supports SMBus ALERT when it is programmed for the Interrupt mode and when the EVENT polarity bit is set to logic 0. The EVENT pin can be ANDed with other EVENT or ALERT signals from other slave devices to signal their intention to communicate with the host controller. When the host detects EVENT or ALERT signal LOW, it issues an Alert Response Address (ARA) to which a slave device would respond with its address. When there are multiple slave devices generating an ALERT the SE98A performs bus arbitration. If it wins the bus, it responds to the ARA and then clears the EVENT pin. Remark: Either in comparator mode or when the SE98A crosses the critical temperature, the host must also read the EVENT status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. Otherwise, the EVENT pin will not get de-asserted. Remark: In the SE98A, the ARA is set to default ON. However, in the SE98B the ARA will be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.
START bit
read Alert Response Address 0 0 1 1 0 0 1
acknowledge device address 0 0 0 1 1 A2
not acknowledge
STOP bit
S host detects SMBus ALERT
0
A1
A0
0
1
P
master sends a START bit, ARA and a read command
Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'.
host NACK and sends a STOP bit
002aab330
Fig 7.
How SE98A responds to SMBus ALERT
SE98A_2
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Product data sheet
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.9 SMBus/I2C-bus interface
The data registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to `00', the location for the Capability register. The Pointer register latches the last location it was set to. Each data register falls into one of three types of user accessibility:
* Read only * Write only * Write/Read same address.
A `write' to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways:
* If the location latched in the Pointer register is correct (most of the time it is expected
that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes.
* If the Pointer register needs to be set, then an address byte, pointer byte,
repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to the timing diagrams in Figure 8, Figure 9, Figure 10 and Figure 11 on how to program the device.
1 SCL SDA S START A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A5
A4
A3
A2
A1
A0 W A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A P ACK STOP by device
002aab308
device address and write
register address
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 8.
SMBus/I2C-bus write to the Pointer register
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
1 SCL SDA S START by host 1 SCL SDA by host D15 A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 W A
D7 ACK by device 8 9 1
D6
D5
D4
D3
D2
D1
D0 A
(cont.)
device address and write 2 3 4 5 6 7
write register address 2 3 4 5 6 7
ACK by device 8 9
D14
D13
D12
D11
D10
D9
D8 A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A P ACK STOP by device by host
002aab412
most significant byte data
least significant byte data
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 9.
SMBus/I2C-bus write to the Pointer register followed by a write data word
1 SCL SDA S START by host 1 SCL SDA SR repeated START by host SCL SDA D15 A6 A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 W A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A
(cont.) ACK by device
device address and write 2 3 4 5 6 7 8
read register address
9 (cont.)
A5
A4
A3
A2
A1
A0 R A ACK by device
(cont.)
device address and read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8 A ACK by host
D7
D6
D5
D4
D3
D2
D1
D0 NA P NACK STOP by host by host
002aab413
returned most significant byte data
returned least significant byte data
A = ACK = Acknowledge bit. NA = Not Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 10. SMBus/I2C-bus write to Pointer register followed by a repeat START and an immediate data word read
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
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NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
1 SCL SDA S START by host 1 SCL SDA D15 A6
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 R A ACK by device
(cont.)
device address and read 2 3 4 5 6 7 8
9
1
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8 A ACK by host
D7
D6
D5
D4
D3
D2
D1
D0 NA P NACK STOP by host
002aab414
returned most significant byte data
returned least significant byte data
A = ACK = Acknowledge bit. NA = Not Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 11. SMBus/I2C-bus word read from register with a pre-set pointer
7.10 Hot plugging
The SE98A can be used in hot plugging applications. Internal circuitry prevents damaging current backflow through the device when it is powered down, but with the I2C-bus, EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The 50 ns noise filter will filter out any insertion glitches from the state machine, which is very robust and not prone to false operation. The device needs a proper power-up sequence to reset itself, not only for the device I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data into its operational registers. The power-up sequence should occur correctly with a fast ramp rate and the I2C-bus active. The SE98A might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. If the SCL line is held LOW, the part will not exit the power-on reset mode since the part is held in reset until SCL is released.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8. Register descriptions
8.1 Register overview
This section describes all the registers used in the SE98A. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold and the ADC, as well as reporting status. The device uses the Pointer register to access these registers. Read registers, as the name implies, are used for read only, and the write registers are for write only. Any attempt to read from a write-only register will result in reading zeroes. Writing to a read-only register will have no effect on the read even though the write command is acknowledged. The Pointer register is an 8-bit register. All other registers are 16-bit.
Table 5. Address n/a 00h 01h 02h 03h 04h 05h 06h 07h 08h to 21h 22h 23h to FFh Register summary POR state n/a 0037h 0000h 0000h 0000h 0000h n/a 1131h A102h 0000h 0000h 0000h Register name Pointer register Capability register (B grade = 0037h) Configuration register Upper Boundary Alarm Trip register Lower Boundary Alarm Trip register Critical Alarm Trip register Temperature register Manufacturer ID register Device ID/Revision register reserved registers SMBus register reserved registers
A write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.2 Capability register (00h, 16-bit read-only)
Table 6. Bit Symbol Reset Access Bit Symbol Reset Access 0 R Table 7. Bit 15:6 5 0 R 7 RFU[1:0] 0 R 0 R 6 0 R 5 VHV 1 R 1 R 0 R 4 TRES[1:0] 0 R Capability register (address 00h) bit allocation 15 14 13 12 RFU[9:2] 0 R 3 0 R 2 WRNG 1 R 0 R 1 HACC 1 R 0 R 0 BCAP 1 R 11 10 9 8
Capability register (address 00h) bit description Symbol RFU VHV Description Reserved for future use. Must be zero. High voltage standoff for pin A0. 1 -- This part can support a voltage up to 10 V on the A0 pin to support JC42.4 ballot 1435.00.
4:3 2 1 0
TRES WRNG HACC BCAP
Temperature resolution. 10 -- 0.125 C LSB (11-bit) Wider range. 1 -- can read temperatures below 0 C and set sign bit accordingly Higher accuracy (set during manufacture). 1 -- B grade accuracy Basic capability. 1 -- has Alarm and Critical Trips interrupt capability.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.3 Configuration register (01h, 16-bit read/write)
Table 8. Bit Symbol Default Access Bit Symbol Default Access 0 R 7 CTLB 0 R/W 0 R 6 AWLB 0 R/W Table 9. Bit 15:11 10:9 Configuration register (address 01h) bit allocation 15 14 13 RFU 0 R 5 CEVNT 0 R/W 0 R 4 ESTAT 0 R/W 0 R 3 EOCTL 0 R/W 0 R/W 2 CVO 0 R/W 12 11 10 HEN[1:0] 0 R/W 1 EP 0 R/W 9 8 SHMD 0 R/W 0 EMD 0 R/W
Configuration register (address 01h) bit description Symbol RFU HEN Description reserved for future use; must be `0'. Hysteresis Enable 00 -- Disable hysteresis (default) 01 -- Enable hysteresis at 1.5 C 10 -- Enable hysteresis at 3 C 11 -- Enable hysteresis at 6 C When enabled, hysteresis is applied to temperature movement around trigger points. For example, consider the behavior of the `Above Alarm Window' bit (bit 14 of the Temperature register) when the hysteresis is set to 3 C. As the temperature rises, bit 14 will be set to 1 (temperature is above the alarm window) when the Temperature register contains a value that is greater than the value in the Alarm Temperature Upper Boundary register. If the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the Alarm Temperature Upper Boundary register minus 3 C. (Refer to Figure 6 and Table 10). Similarly, the `Below Alarm Window' bit (bit 13 of the Temperature register) will be set to 0 (temperature is equal to or above the Alarm Window Lower Boundary Trip register) when the value in the Temperature register is equal to or greater than the value in the Alarm Temperature Lower Boundary register. As the temperature decreases, bit 13 will be set to 1 when the value in the Temperature register is equal to or less than the value in the Alarm Temperature Lower Boundary register minus 3 C. Note that hysteresis is also applied to EVENT pin functionality. When either of the Critical Trip or Alarm Window lock bits is set, these bits cannot be altered until unlocked.
8
SHMD
Shutdown Mode. 0 -- Enabled Temperature Sensor (default) 1 -- Disabled Temperature Sensor When shut down, the thermal sensor diode and Analog-to-Digital Converter (ADC) are disabled to save power, no events will be generated. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be set until unlocked. However, it can be cleared at any time.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Configuration register (address 01h) bit description ...continued Symbol CTLB Description Critical Trip Lock bit. 0 -- Critical Alarm Trip register is not locked and can be altered (default). 1 -- Critical Alarm Trip register settings cannot be altered. This bit is initially cleared. When set, this bit will return a 1, and remains locked until cleared by internal Power-on reset. This bit can be written with a single write and do not require double writes.
Table 9. Bit 7
6
AWLB
Alarm Window Lock bit. 0 -- Upper and Lower Alarm Trip registers are not locked and can be altered (default). 1 -- Upper and Lower Alarm Trip registers setting cannot be altered. This bit is initially cleared. When set, this bit will return a 1 and remains locked until cleared by internal power-on reset. This bit can be written with a single write and does not require double writes.
5
CEVNT
Clear EVENT (write only). 0 -- No effect (default). 1 -- Clears active EVENT in Interrupt mode. Writing to this register has no effect in Comparator mode. When read, this register always returns zero.
4
ESTAT
EVENT Status (read only). 0 -- EVENT output condition is not being asserted by this device (default). 1 -- EVENT output pin is being asserted by this device due to Alarm Window or Critical Trip condition. The actual event causing the EVENT can be determined from the Read Temperature register. Interrupt Events can be cleared by writing to the `Clear EVENT' bit (CEVNT). Writing to this bit will have no effect.
3
EOCTL
EVENT Output Control. 0 -- EVENT output disabled (default). 1 -- EVENT output enabled. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
2
CVO
Critical Event Only. 0 -- EVENT output on Alarm or Critical temperature event (default) 1 -- EVENT only if temperature is above the value in the critical temperature register When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered until unlocked.
*
Advisory note: - JEDEC specification requires only the Alarm Window lock bit to be set. - Work-around: Clear both Critical Trip and Alarm Window lock bits. - Future 1.7 V to 3.6 V SE98B will require only the Alarm Window lock bit to be set.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Configuration register (address 01h) bit description ...continued Symbol EP Description EVENT Polarity. 0 -- active LOW (default). 1 -- active HIGH. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
Table 9. Bit 1
0
EMD
EVENT Mode. 0 -- comparator output mode (default) 1 -- interrupt mode When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
Table 10. Action
Hysteresis enable Below Alarm Window bit (bit 13) Temperature slope Threshold temperature Ttrip(l) - Thys Ttrip(l) Above Alarm Window bit (bit 14) Temperature slope rising falling Threshold temperature Ttrip(u) Ttrip(u) - Thys Above Critical Trip bit (bit 15) Temperature slope rising falling Threshold temperature Tth(crit) Tth(crit) - Thys
sets clears
falling rising
current temperature temperature
critical alarm threshold hysteresis
upper alarm threshold hysteresis
lower alarm threshold hysteresis
time Above Critical Trip (register 05h; bit 15 = ACT bit) Above Alarm Window (register 05h; bit 14 = AAW bit) Below Alarm Window (register 05h; bit 13 = BAW bit) clear set clear
clear
set
clear
set
clear
002aac799
Fig 12. Hysteresis: how it works
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.4 Temperature format
The 16-bit value used in the following Trip Point Set and Temperature Read-Back registers is 2's complement with the Least Significant Bit (LSB) equal to 0.0625 C. For example:
* A value of 019Ch will represent 25.75 C * A value of 07C0h will represent 124 C * A value of 1E64h will represent -25.75 C.
The resolution is 0.125 C. The unused LSB (bit 0) is set to `0'. Bit 11 will have a resolution of 128 C. The upper 3 bits of the temperature register indicate Trip Status based on the current temperature, and are not affected by the status of the EVENT output. Table 11 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b.
Table 11. Degree Celsius and Temperature Data register Content of Temperature Data register Status bits = 000b Binary +125 C +25 C +1 C +0.25 C +0.125 C 0 C -0.125 C -0.25 C -1 C -20 C -25 C -55 C Hex 07D0h 0190h 0010h 0004h 0002h 0000h 1FFEh 1FFCh 1FF0h 1F40h 1E70h 1C90h Status bits = 111b Binary Hex E7D0h E190h E010h E004h E002h E000h FFFEh FFFCh FFF0h FF40h FE70h FC90h
Temperature
000 0 01111101 000 0 000 0 00011001 000 0 000 0 00000001 000 0 000 0 00000000 010 0 000 0 00000000 001 0 000 0 00000000 000 0 000 1 11111111 111 0 000 1 11111111 110 0 000 1 11111111 000 0 000 1 11110100 000 0 000 1 11100111 000 0 000 1 11001001 000 0
111 0 01111101 000 0 111 0 00011001 000 0 111 0 00000001 000 0 111 0 00000000 010 0 111 0 00000000 001 0 111 0 00000000 000 0 111 1 11111111 111 0 111 1 11111111 110 0 111 1 11111111 000 0 111 1 11110100 000 0 111 1 11100111 000 0 111 1 11001001 000 0
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.5 Temperature Trip Point registers
8.5.1 Upper Boundary Alarm Trip register (16-bit read/write)
The value is the upper threshold temperature value for Alarm mode. The data format is 2's complement with bit 2 = 0.25 C. `RFU' bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity.
Table 12. Bit Symbol Reset Access Bit Symbol Reset Access Table 13. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Upper Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 UBT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 UBT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Upper Boundary Alarm Trip register bit description Symbol RFU SIGN UBT RFU Description reserved; always 0 Sign (MSB) Upper Boundary Alarm Trip Temperature (LSB = 0.25 C) reserved; always 0
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.5.2 Lower Boundary Alarm Trip register (16-bit read/write)
The value is the lower threshold temperature value for Alarm mode. The data format is 2's complement with bit 2 = 0.25 C. RFU bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity.
Table 14. Bit Symbol Reset Access Bit Symbol Reset Access Table 15. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 LBT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 LBT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Lower Boundary Alarm Trip register bit description Symbol RFU SIGN LBT RFU Description reserved; always 0 Sign (MSB) Lower Boundary Alarm Trip Temperature (LSB = 0.25 C) reserved; always 0
8.5.3 Critical Alarm Trip register (16-bit read/write)
The value is the critical temperature. The data format is 2's complement with bit 2 = 0.25 C. RFU bits will always report zero.
Table 16. Bit Symbol Reset Access Bit Symbol Reset Access Table 17. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 CT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 CT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Critical Alarm Trip register bit description Symbol RFU SIGN CT RFU Description reserved; always 0 Sign (MSB) Critical Alarm Trip Temperature (LSB = 0.25 C) reserved; always 0
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.6 Temperature register (16-bit read-only)
Table 18. Bit Symbol Reset Access Bit Symbol Reset Access Table 19. Bit 15 0 R 0 R 0 R Temperature register bit allocation 15 ACT 0 R 7 14 AAW 0 R 6 13 BAW 0 R 5 12 SIGN 0 R 4 TEMP[6:0] 0 R 0 R 0 R 0 R 0 R 3 11 10 0 R 2 9 0 R 1 8 0 R 0 RFU 0 R TEMP[10:7]
Temperature register bit description Symbol ACT Description Above Critical Trip. Increasing Tamb: 0 -- Tamb < Tth(crit) 1 -- Tamb Tth(crit) Decreasing Tamb: 0 -- Tamb < Tth(crit) - Thys 1 -- Tamb Tth(crit) - Thys
14
AAW
Above Alarm Window. Increasing Tamb: 0 -- Tamb Ttrip(u) 1 -- Tamb > Ttrip(u) Decreasing Tamb: 0 -- Tamb Ttrip(u) - Thys 1 -- Tamb > Ttrip(u) - Thys
13
BAW
Below Alarm Window. Increasing Tamb: 0 -- Tamb Ttrip(l) 1 -- Tamb < Ttrip(l) Decreasing Tamb: 0 -- Tamb Ttrip(l) - Thys 1 -- Tamb < Ttrip(l) - Thys
12
SIGN
Sign bit. 0 -- positive temperature value 1 -- negative temperature value
11:1 0
TEMP RFU
Temperature Value (2's complement). (LSB = 0.125 C) reserved; always 0
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.7 Manufacturer's ID register (16-bit read-only)
The manufacture's ID matches that assigned to NXP Semiconductors PCI-SIG (1131h), and is intended for use to identify the manufacturer of the device.
Table 20. Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 1 R 0 R 7 0 R 6 0 R 5 Manufacturer's ID register bit allocation 15 14 13 12 1 R 4 1 R 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 1 R 0 1 R Manufacturer ID
(continued)
8.8 Device ID register
The device ID and device revision are A1h and 02h, respectively.
Table 21. Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 1 R 7 0 R 6 1 R 5 0 R 4 0 R Device ID register bit allocation 15 14 13 12 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 1 R 8 1 R 0 0 R Device ID
Device revision
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
8.9 SMBus register
Table 22. Bit Symbol Reset Access Bit Symbol Reset Access Table 23. Bit 15:8 7 0 R 7 STMOUT 0 R/W 0 R 0 R 0 R 0 R 6 0 R 5 0 R 4 RFU 0 R 0 R 0 R SMBus Time-out register bit allocation 15 14 13 12 RFU 0 R 3 0 R 2 0 R 1 0 R 0 SALRT 0 R/W 11 10 9 8
SMBus Time-out register bit description Symbol RFU STMOUT Description reserved; always 0 SMBus time-out. 0 -- SMBus time-out is enabled (default) 1 -- disable SMBus time-out When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
6:1 0
RFU SALRT
reserved; always 0 SMBus ALERT. 0 -- SMBus ALERT is enabled (default) 1 -- disable SMBus ALERT When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
9. Application design-in information
In a typical application, the SE98A behaves as a slave device and interfaces to the master (or host) via the SCL and SDA lines. The host monitors the EVENT output pin, which is asserted when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to the shared SPD's A0, A1 and A2 pins, otherwise they must be pulled HIGH or LOW. The SDA and SCL serial interface pins are open-drain and require pull-up resistors, and are able to sink a maximum current of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are 10 k, but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus.
slave VDD SCL SPD A0 A1 A2 SDA A0 A1 A2 VDD SCL
10 k (3x)
master
SE98A
SDA EVENT
HOST CONTROLLER
VSS
VSS
002aad900
Fig 13. Typical application
mother board 3.3 V
0.1 F 0.1 F 0.1 F 10 k 10 k 10 k 10 k
1.1 V VCC(B) VCC(A) B2 A2
VDD
SCL
SCL SDA EVENT HOST CONTROLLER
SE98A
A0 A1 A2
SDA EVENT
PCA9509
B1 A1
VSS
EN
002aad759
Fig 14. SE98A interfacing with 1.1 V host controller
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
9.1 SE98A in memory module application
Figure 15 shows the SE98A being placed in the memory module application with the SPD. The SE98A is centered in the memory module to provide the function to monitor the temperature of the DRAM. In the event of overheat, the SE98A triggers the EVENT output and the memory controller can throttle the memory bus to slow the DRAM, or the CPU can increase the refresh rate for the DRAM. The memory controller can also read the SE98A and watch the DRAM thermal behavior.
DIMM SPD DRAM DRAM DRAM DRAM
SE98A
SDA SMBus SCL EVENT
MEMORY CONTROLLER
CPU
002aad760
Fig 15. System application
9.2 Layout consideration
The SE98A does not require any additional components other than the host controller to measure temperature. A 0.1 F bypass capacitor between the VDD and VSS pins is located as close as possible to the power and ground pins for noise protection.
9.3 Thermal considerations
In general, self-heating is the result of power consumption and not a concern, especially with the SE98A, which consumes very low power. In the event the SDA and EVENT pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 C. Equation 1 is the formula to calculate the effect of self-heating: T = R th ( j-a ) x [ ( V DD x I DD ( AV ) ) + ( V OL ( SDA ) x I OL ( sin k ) ( SDA ) ) + ( V OL ( EVENT ) x I OL ( sin k )EVENT ) ] where: T = Tj - Tamb Tj = junction temperature Tamb = ambient temperature Rth(j-a) = package thermal resistance VDD = supply voltage IDD(AV) = average supply current VOL(SDA) = LOW-level output voltage on pin SDA VOL(EVENT) = LOW-level output voltage on pin EVENT
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
IOL(sink)(SDA) = SDA output current LOW IOL(sink)EVENT = EVENT output current LOW
10. Limiting values
Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn VA0 Isink Tj(max) Tstg Parameter supply voltage voltage on any other pin voltage on pin A0 sink current maximum junction temperature storage temperature SDA, SCL, EVENT pins overvoltage input; A0 pin at SDA, SCL, EVENT pins Conditions Min -0.3 -0.3 -0.3 -1 -65 Max +4.2 +4.2 +12.5 +50.0 150 +165 Unit V V V mA C C
11. Characteristics
Table 25. Characteristics VDD = 1.7 V to 3.6 V; Tamb = -40 C to +125 C; unless otherwise specified. Symbol Tacc Parameter temperature accuracy Conditions B grade temperature accuracy; VDD = 1.7 V to 3.6 V Tamb = 75 C to 95 C Tamb = 40 C to 125 C Tamb = -40 C to +125 C Tres IDD(AV) IDD(stb) Tconv Ef(conv) ILIL Ipd ZIL ZIH VDD temperature resolution average supply current standby supply current conversion period conversion rate error percentage error in programmed data internal; pins A0, A1, A2; VI = 0.3VDD to VDD pins A0, A1, A2; VI < 0.3VDD pins A0, A1, A2; VI 0.3VDD SMBus inactive -1.0 -2.0 -3.0 -30 -1.0 0.05 30 800 1.7 < 0.5 < 1 < 2 0.125 250 0.1 100 1.8 or 2.5 or 3.3 +1.0 +2.0 +3.0 400 5 120 +30 +1.0 4.0 3.6 C C C C A A ms % A A k k V Min Typ Max Unit
LOW-level input leakage current pins A0, A1, A2; VI = VSS pull-down current LOW-level input impedance HIGH-level input impedance supply voltage
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Table 26. SMBus DC characteristics VDD = 1.7 V to 3.6 V; Tamb = -20 C to +120 C; unless otherwise specified. These specifications are guaranteed by design. Symbol VIH VIL VI(ov) Vth(POR)H Vth(rec)POR IOL(sink)EVENT IOL(sink)(SDA) ILOH ILIH ILIL Ci
[1]
Parameter HIGH-level input voltage LOW-level input voltage overvoltage input voltage HIGH-level power-on reset threshold voltage power-on reset recovery threshold voltage LOW-level output sink current on pin EVENT LOW-level output sink current on pin SDA HIGH-level output leakage current HIGH-level input leakage current LOW-level input leakage current input capacitance
Conditions SCL, SDA; VDD = 1.7 V to 3.6 V SCL, SDA; VDD = 1.7 V to 3.6 V pin A0; VI(ov) - VDD > 4.8 V
[1]
Min 0.7VDD 7.0 -
Typ 5
Max VDD + 1 0.3VDD 10 1.7 0.5 1.0 +1.0 +1.0 10
Unit V V V V V mA mA A A A pF
for device reset VOL = 0.4 V VOL = 0.5 V VOH = VDD pins SCL, SDA; VI = VDD or VSS pins SCL, SDA; VI = VDD or VSS SCL, SDA pins
6 3 -1.0 -1.0 -
High-voltage input voltage applied to pin A0 during RWP and CRWP operations of the equivalent SPD-included parts. The JEDEC specification is 7 V (min.) and 10 V (max.). When VDD is 3.6 V, then VI(ov) > 4.8 V + VDD or > 4.8 V + 3.6 V then the minimum voltage is 8.4 V.
350 IDD(AV) (A) 250
002aae374
350 IDD(AV) (A) 250
002aae375
VDD = 3.6 V 3.0 V 2.3 V 1.7 V
VDD = 3.6 V 3.0 V 2.3 V 1.7 V
150
150
50 -50
-25
0
25
50
75
125 100 Tamb (C)
50 -50
-25
0
25
50
75
125 100 Tamb (C)
a. I2C-bus inactive Fig 16. Average supply current
b. I2C-bus active
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
5 Isd(VDD) (A) 3 VDD = 3.6 V 3.0 V 2.3 V 1.7 V 1
002aad881
Tacc (C)
3.0 2.0 1.0 0
002aae376
-1.0 -2.0
-1 -40
0
40
80
120 Tamb (C)
-3.0 -50
-25
0
25
50
75
100 125 Tamb (C)
I2C-bus and temp sensor inactive.
VDD = 1.7 V to 3.6 V.
Fig 17. Shutdown supply current
30 IOL(sink)EVENT (mA) 20
002aae377
Fig 18. Typical temperature accuracy
30 IOL(sink)SDA (mA) 20 VDD = 3.6 V 3.0 V 2.3 V 1.7 V
002aae378
10 VDD = 3.6 V 3.0 V 2.3 V 1.7 V -25 0 25 50 75 125 100 Tamb (C)
10
0 -50
0 -50
-25
0
25
50
75
125 100 Tamb (C)
VOL = 0.4 V.
VOL = 0.5 V.
Fig 19. EVENT output current
15 conversion rate (conv/s) 13
002aad886
Fig 20. SDA output current
140 Tconv (ms) 120
002aad887
11 100 9 80
7
5 -40
0
40
80
120 Tamb (C)
60 -40
0
40
80
120 Tamb (C)
VDD = 3.0 V to 3.6 V.
VDD = 3.0 V to 3.6 V.
Fig 21. Conversion rate
Fig 22. Conversion period
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
3.0 Vth (V) 2.5
002aad889
120 thermal response (%) 80
(1)
002aad891
2.0 40 1.5
(2)
1.0 -40
0
40
80
120 Tamb (C)
0 0 1 2 3 4 time (s) 5
For temp sensor conversion.
From 25 C (air) to 120 C (oil bath). (1) TSSOP8 (2) HWSON8
Fig 23. Average power-on threshold voltage
5 temp error (C) 3
Fig 24. Package thermal response
002aad892
1
-1 102
103
104
105
106
107 108 noise frequency (Hz)
VDD = 3.3 V + 150 mV (p-p); 0.1 F AC coupling capacitor; no decoupling capacitor; Tamb = 25 C.
Fig 25. Temperature error versus power supply noise frequency
3.0 Ipd (A) 2.0 VDD = 3.6 V 3.0 V 2.3 V 1.7 V 1.0
002aae379
3.0 Ipd (A) 2.0 VDD = 3.6 V 3.0 V 2.3 V 1.7 V 1.0
002aae380
0 -50
-25
0
25
50
75
125 100 Tamb (C)
0 -50
-25
0
25
50
75
125 100 Tamb (C)
a. VI = 0.3VDD; pins A0, A1, A2 Fig 26. Typical pull-down current
SE98A_2
b. VI = 0.7VDD; pins A0, A1, A2
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Product data sheet
Rev. 02 -- 6 August 2009
32 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Table 27. SMBus AC characteristics VDD = 1.7 V to 3.6 V; Tamb = -40 C to +125 C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz. Symbol fSCL tHIGH tLOW tto(SMBus) tr tf tSU;DAT th(i)(D) tHD;DAT tSU;STA tHD;STA tSU;STO tBUF tSP Parameter SCL clock frequency HIGH period of the SCL clock 70 % to 70 % LOW period of the SCL clock 30 % to 30 % SMBus time-out time rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data input hold time data hold time set-up time for a repeated START condition hold time (repeated) START condition set-up time for STOP condition bus free time between a STOP and START condition pulse width of spikes that must be suppressed by the input filter data valid time output fall time power-on reset pulse time power supply falling from clock
[2] [2][3] [4] [5]
Conditions
Standard mode Min 10[1] 4000 4700 25 250 0 200 4700 4000 4000 4700 Max 100 35 1000 300 3450 50
Fast mode Min 10[1] 600 1300 25 20 100 0 200 600 600 600 1300 Max 400 35 300 300 900 50
Unit kHz ns ns ms ns ns ns ns ns ns ns ns ns ns
LOW period to reset SMBus
30 % of SDA to 70 % of SCL
[6]
tVD;DAT tf(o) tPOR
[1] [2] [3] [4] [5] [6]
200 0.5
-
200 0.5
250 -
ns ns s
Minimum clock frequency is 0 kHz if SMBus Time-out is disabled. Delay from SDA STOP to SDA START. A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Delay from SCL HIGH-to-LOW transition to SDA edges. Delay from SCL LOW-to-HIGH transition to restart SDA. Delay from SDA START to first SCL HIGH-to-LOW transition.
SE98A_2
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Product data sheet
Rev. 02 -- 6 August 2009
33 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
tLOW tr SCL tBUF tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;DAT VIH VIL P S S P tSU;STO tf VIH VIL
SDA
SCL tSU;STO tSU;STA
VIH VIL
SDA tW STOP condition write cycle START condition
VIH VIL
002aae750
S = START condition P = STOP condition
Fig 27. AC waveforms
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
34 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1
E D
A X
c y HE Z vMA
8
5
A2 A1 pin 1 index Lp L detail X
(A3)
A
1
e bp
4
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.13 D(1) 3.1 2.9 E(2) 4.5 4.3 e 0.65 HE 6.5 6.3 L 0.94 Lp 0.7 0.5 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-24 03-02-18
Fig 28. Package outline SOT530-1 (TSSOP8)
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Product data sheet
Rev. 02 -- 6 August 2009
35 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm
SOT1069-1
X
b D
v
M
AB A
B
E
A A1
terminal 1 index area 1/2 e terminal 1 index area L e
1 4
detail X C y1 C y
(8x)
Eh
8
5
Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A(1) 0.8 A1 0.04 b 0.3 0.2 D 2.1 2.0 1.9 D1 1.6 1.4 E 3.1 3.0 2.9 E1 1.6 0.5 1.4 0.35 e 1 scale L 0.45 0.1 0.05 0.05 v y y1 2 mm
Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 OUTLINE VERSION SOT1069-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 08-06-11 08-07-10
Fig 29. Package outline SOT1069-1 (HWSON8)
SE98A_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
36 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
HXSON8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm
SOT1052-1
X
b D
v
M
AB A
B
E
A
A1
detail X terminal 1 index area 1/2 e terminal 1 index area L e
1 4
C y1 C y
(8x)
Eh
8
5
Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A(1) 0.5 A1 0.04 b 0.3 0.2 D 2.1 2.0 1.9 D1 1.6 1.4 E 3.1 3.0 2.9 E1 1.6 0.5 1.4 0.35 e 1 scale L 0.45 0.1 0.05 0.05 v y y1 2 mm
Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 OUTLINE VERSION SOT1052-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 08-01-11 08-03-11
Fig 30. Package outline SOT1052-1 (HXSON8)
SE98A_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
37 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
SE98A_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
38 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 28 and 29
Table 28. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 29. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 31.
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
39 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 30. Acronym ADC ARA BIOS CDM CMOS CPU CRWP DDR DDR2 DDR3 DIMM DRAM ESD HBM I2C-bus I/O LSB MM MSB
SE98A_2
Abbreviations Description Analog-to-Digital Converter Alert Response Address Basic Input/Output System Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit Clear Reversible Write Protection Double Data Rate Double Data Rate 2 Double Data Rate 3 Dual In-line Memory Module Dynamic Random Access Memory ElectroStatic Discharge Human Body Model Inter IC bus Input/Output Least Significant Bit Machine Model Most Significant Bit
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
40 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Abbreviations ...continued Description Registered Dual In-line Memory Module Small Outline Dual In-line Memory Module Personal Computer Power-On Reset Reversible Write Protection System Management Bus Serial Presence Detect
Table 30. Acronym RDIMM SO-DIMM PC POR RWP SMBus SPD
15. Revision history
Table 31. SE98A_2 Modifications: Revision history Release date 20090806 Data sheet status Product data sheet 3rd Change notice 1st Supersedes SE98A_1 sentence: appended "using an open-drain output Document ID
* * * *
Section 1 "General description", paragraph, that can be pulled up between 0.9 V and 3.6 V". Section 2 "Features": 1st bullet item re-written.
Table 1 "Ordering information", Table note [1]: changed from "JEDEC WCE-3, TDFN" to "JEDEC VCED-3 PSON8" Section 7.3.2.1 "Alarm window": - 1st Advisory notification, Competitor device: appended "(CEVNT)" to end of phrase - 1st Advisory notification, Work-around: appended "(CEVNT)" to end of phrase - 2nd Advisory notification, Competitor devices: changed from "... when new UPPER or LOWER and Event bit 3 (EOCTL) are set ... " to "when new UPPER or LOWER Alarm Windows and the EVENT output are set ..." - 2nd Advisory notification, Work-around: appended "(EOCTL = 1)" to end of phrase
*
Section 7.3.2.2 "Critical trip" - 1st paragraph, last sentence: changed from "... through the Clear EVENT bit ..." to "... through the Clear EVENT bit (CEVNT) ... - Advisory notification, Competitor devices: re-written - Advisory notification, Work-around: changed from "Wait at least 125 ms before enabling EVENT output, Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before Event bit 3 (EOCTL) is enabled and Event value is checked." to "Wait at least 125 ms before enabling EVENT output (EOCTL = 1), Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before EVENT output is enabled and Event value is checked.
* * * * *
SE98A_1
Section 7.7 "SMBus Time-out": added second "Remark" statement. Section 7.8 "SMBus ALERT": added second "Remark" statement. Section 9.3 "Thermal considerations": symbols used in Equation 1 are updated to match those used in characteristics tables (old) Table 27 "SMBus AC characteristics" replaced in its entirety by (new) Table 27 "SMBus AC characteristics" (old) Figure 27 "Definition of timing for F/S-mode devices on the I2C-bus" replaced by Figure 27 "AC waveforms" Product data sheet -
20090305
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
41 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
SE98A_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 August 2009
42 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
18. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.3 7.3.3.1 7.3.3.2 7.4 7.4.1 7.5 7.6 7.7 7.8 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Serial bus interface . . . . . . . . . . . . . . . . . . . . . . 5 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 5 EVENT output condition . . . . . . . . . . . . . . . . . . 6 EVENT pin output voltage levels and resistor sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 6 EVENT thresholds . . . . . . . . . . . . . . . . . . . . . . 8 Alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Event operation modes . . . . . . . . . . . . . . . . . . . 9 Comparator mode. . . . . . . . . . . . . . . . . . . . . . . 9 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Conversion rate. . . . . . . . . . . . . . . . . . . . . . . . 10 What temperature is read when conversion is in progress . . . . . . . . . . . . . . . . 10 Power-up default condition . . . . . . . . . . . . . . . 11 Device initialization . . . . . . . . . . . . . . . . . . . . . 11 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . 12 SMBus ALERT . . . . . . . . . . . . . . . . . . . . . . . . 12 SMBus/I2C-bus interface . . . . . . . . . . . . . . . . 13 Hot plugging . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register descriptions . . . . . . . . . . . . . . . . . . . 16 Register overview . . . . . . . . . . . . . . . . . . . . . . 16 Capability register (00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 17 Configuration register (01h, 16-bit read/write) . . . . . . . . . . . . . . . . . . 18 Temperature format . . . . . . . . . . . . . . . . . . . . 21 Temperature Trip Point registers . . . . . . . . . . . 22 Upper Boundary Alarm Trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 22 Lower Boundary Alarm Trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 23 Critical Alarm Trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 23 Temperature register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 24 8.7 8.8 8.9 9 9.1 9.2 9.3 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 Manufacturer's ID register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . Device ID register. . . . . . . . . . . . . . . . . . . . . . SMBus register. . . . . . . . . . . . . . . . . . . . . . . . Application design-in information . . . . . . . . . SE98A in memory module application . . . . . . Layout consideration . . . . . . . . . . . . . . . . . . . Thermal considerations . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 27 28 28 28 29 29 35 38 38 38 38 39 40 41 42 42 42 42 42 42 43
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 August 2009 Document identifier: SE98A_2

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